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Workshop on Open-Source EDA Technology (WOSET)

WOSET 2020 Schedule

The video presentations for each paper are available on the WOSET YouTube Playlist.

Please watch the videos prior to the Q&A!

Each time will be a Q&A with the presenting author via the workshop Zoom call. For the short papers, discussion will be chat in the WOSET Slack Workspace. Please register through ICCAD (for free!) to participate in the Zoom or Slack discussions.

Session 1

Time (GMT) Time (PST) Article # Author(s) Title
5:00 PM 9:00 AM 3 Edwards Google/SkyWater and the Promise of the Open PDK
5:15 PM 9:15 AM 9 Agiza, Reda OpenPhySyn: An Open-Source Physical Synthesis Optimization Toolkit
5:30 PM 9:30 AM 21 Ghazy, Shalan OpenLANE: The Open-Source Digital ASIC Implementation Flow
5:45 PM 9:45 AM 12 Agarwal, Ataei, He, Hua, Lu, Maleki, Yang, Pingali, Manohar Digital Flow for Asynchronous VLSI Systems: Status Update
6:00 PM 10:00 AM 7 He, Yang, Manohar A power router for gridded cell placement
6:15 PM 10:15 AM 18 Hasler, Natarajan An Open-source ToolSet for FPAA Design
6:30 PM 10:30 AM 4 Gamal, Gouhar, Shalan A Push-button Idea to GDS-II SoC Design Flow

Short Papers

Time (GMT) Time (PST) Article # Author(s) Title
6:45-7:45PM 10:45-11:45AM 1 Maleki, Agarwal, Pingali Hypergraph Partitioning via Geometric Embeddings
6:45-7:45PM 10:45-11:45AM 2 Schoeberl, Andersen, Rasmussen, Lin Towards an Open-Source Verification Method with Chisel and Scala
6:45-7:45PM 10:45-11:45AM 5 Bailey CVC: Circuit Validity Checker An open source netlist reliabilty verification system
6:45-7:45PM 10:45-11:45AM 6 Sossou, Edwards An Open Source Alternative to Wire Bonding
6:45-7:45PM 10:45-11:45AM 8 Ozdemir, Seibert, Khasawneh, Madden A PostScript Toolkit for Electronic Design
6:45-7:45PM 10:45-11:45AM 11 Huang Taskflow: A General-purpose Parallel and Heterogeneous Task Programming System for VLSI CAD
6:45-7:45PM 10:45-11:45AM 13 Goettsch An Automatic Schematic Generation Tool for SPICE Netlists
6:45-7:45PM 10:45-11:45AM 14 Zhang, Dai, Ma, Lin, Luo Cocoon: An Open Source Infrastructure for Integrated EDA with Interoperability and Interactivity
6:45-7:45PM 10:45-11:45AM 16 Rodriguez, Barrera, Giesen, Jover, Kosmidis Facilitating the Specification and Implementation of Pipelined Designs with Skeletor
6:45-7:45PM 10:45-11:45AM 20 Kindgren Edalize it. Don’t critizise it
6:45-7:45PM 10:45-11:45AM 23 Rakheja Automatically Building Digital Symbol Libraries

Session 2

Time (GMT) Time (PST) Article # Author(s) Title
7:45 PM 11:45 AM 22 Guo, Luo Pillars: An Integrated CGRA Design Framework
8:00 PM 12:00 PM 24 Castro-Godinez, Barrantes-Garcia, Shafique, Henkel AxLS: An Open-Source Framework for Netlist Transformation Approximate Logic Synthesis
8:15 PM 12:15 PM 10 Dargelas, Zeller Universal Hardware Data Model
8:30 PM 12:30 PM 25 Pal, Dodeja, Kumar, Vasudevan GOLDMINE: A tool for enhancing verification productivity
8:45 PM 12:45 PM 15 Ballance PyVSC: SystemVerilog-Style Constraints, and Coverage in Python
9:00 PM 1:00 PM 19 Tang, Gore, Giacomin, Alacchi, Chauviere, Gaillardon OpenFPGA: Towards Automated Prototyping for Versatile FPGAs
9:15 PM 1:15 PM 17 Temple, Neto, Austin, Tang, Gaillardon LSOracle: Using Mixed Logic Synthesis in an Open Source ASIC Design Flow