WOSET 2021 Schedule
November 4, 2021
All short paper videos in a given time slot will be shown sequentially followed by a 5 or 6 minute Q&A with the authors. Long paper videos in a given time slot will also be shown sequentially followed by a 6 minute Q&A with the authors. Poster presentations will last 5 minutes each.
Short Papers
| Time (GMT) |
Time (PDT) |
Article # |
Author(s) |
Title |
| 4:00 PM |
9:00 AM |
15 |
Healy, Yu, Dao, Chung, Koch |
FABulous: an Open-Everything Framework for Embedded FPGAs |
| 21 |
Dogan, Ugurdag, Guthaus |
OpenCache: An Open-Source OpenRAM Based Cache Generator |
| 4:15 PM |
9:15 AM |
14 |
Yuan, Shukla, Chetoui, Knox, Nemtzow, Reda, Coskun |
Towards Fast and Accurate Parallel Chip Thermal Simulations with PACT |
| 22 |
Garg, Wang, Coffman, Renau |
A Guide for Rapid Creation of New HDLs |
| 4:30 PM |
9:30 AM |
9 |
Zeller |
SystemVerilog IDE integration with Verible Language Server support |
| 10 |
Fajardo, Laeufer, Bachrach, Sen |
RTLFuzzLab |
| 13 |
He, Hua, Lu, Maleki, Yang, Pingali, Manohar |
interact: An Interactive Design Environment for Asynchronous Logic |
Long Papers 1
| Time (GMT) |
Time (PDT) |
Article # |
Author(s) |
Title |
| 4:51 PM |
9:51 AM |
1 |
Callahan, Ansell, Bushagour, Green, Lattimore, Callaghan |
CFU Playground: Build your own ML Processor using Open Source |
| 2 |
Schwartz, Sharma, Rad, Takusagawa, Stoy, Nikhil |
The Open-Source Bluespec bsc Compiler and Reusable Example Designs |
| 5:21 PM |
10:21 AM |
11 |
Hasler, Muldrey, Hardy |
A CMOS Programmable Analog Standard Cell Library in Skywater 130nm Open-Source Process |
| 4 |
Edwards |
Automating GDS Generation in Magic |
| 5:51 PM |
10:51 AM |
5 |
Euphrosine, Springer |
Porting software to hardware using XLS/DSLX |
| 6 |
Eldridge, Barua, Chapyzhenka, Izraelevitz, Koenig, Lattner, Lenharth, Leontiev, Schuiki, Sunder, Young, Xia |
MLIR as Hardware Compiler Infrastructure |
| 6:21 PM |
11:21 AM |
9 minute break |
Poster Presentations
Long Papers 2
| Time (GMT) |
Time (PDT) |
Article # |
Author(s) |
Title |
| 6:50 PM |
11:50 AM |
7 |
Berlstein, Nigam, Gyurgyik, Sampson |
A Toolkit for Designing Hardware DSLs |
| 12 |
Temple, Snelgrove, Neto, Gaillardon |
LSOracle 2.0: Capabilities, Integration, and Performance |
| 7:20 PM |
12:20 PM |
3 |
Laeufer, Bachrach, Sen |
Open-Source Formal Verification for Chisel |
| 8 |
Dobis, Petersen, Schoeberl |
Towards Functional Coverage-Driven Fuzzing for Chisel Designs |
| 7:50 PM |
12:50 PM |
20 |
Wang, Garg, Coffman, Mayer, Renau |
A Parallel HDL Compilation Framework |
| 23 |
Beamer, Nijssen, Pandian, Zhang |
ESSENT: A High-Performance RTL Simulator |