woset-workshop

Workshop on Open-Source EDA Technology (WOSET)

Time (PST)	Duration (Minutes)	Article #	Author(s)	Title
8:00 AM	20	12	Wijerathne, Li, Karunarathne, Mitra, Peh	Morpher: An Open-Source Integrated Compilation and Simulation Framework for CGRA
8:20 AM	20	20	Xu, Xiao, Luo, Liang	A MLIR-Based Hardware Synthesis Framework
8:40 AM	20	2	Euphrosine	Accelerate Silicon Design with Jupyter Notebooks
9:00 AM	20	10	Zhu, Yin, Wang, Tan	GreenRio: A Modern RISC-V Microprocessor Completely Designed with An Agile Open-source EDA Flow
9:20 AM	20	5	Goldstein, Edwards	Accessibility of Chip Design to the Non-Professional
9:40 AM	20	18	Liang, Edwards	IRSIM: A Switch-Level Simulator and Dynamic Power Analysis Tool

Time (PST)	Duration (Minutes)	Article #	Author(s)	Title
10:00 AM	60	4	Kashif, Ahmed, Karim	Bitstream Chef
		6	Shahzaib, Kashif, Ahmed, Karim	SoC-Now: An Open-Source Web based RISC-V SoC Generator
		7	Jia, Luo, Lu, Liang	TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra
		8	Ahmed, Cirimelli-Low, Guthaus	OpenRegFile: Open-Source Register File Generation
		13	Schoeberl, Pezzarossa	From Chisel to Chips with Open-Source Tools
		16	Jayaraman, Huang, Renau	The Hardware Interchange Format
		17	Kemmerer	PipelineC: Easy open-source hardware description between RTL and HLS

Time (PST)	Duration (Minutes)	Article #	Author(s)	Title
11:00 AM	20	1	Birch	Open source FPGA-based emulation with Nexus
11:20 AM	20	11	Eriksson, Vora	A Java Backend for ESSENT
11:40 AM	20	19	Korbel	Rapid Open Hardware Development Framework
12:00 PM	20	3	Agostini, Curzel, Limaye, Amatya, Minutoli, Castellana, Manzano, Ferrandi, Tumeo	SODA Synthesizer: an Open-Source, End-to-End Hardware Compiler
12:20 PM	20	15	Hugg	8bitworkshop: An Interactive Verilog Learning Tool
12:40 PM	20	9	Manohar	xcell: a cell library characterizer for combinational and state-holding gates
1:00 PM	20	14	Nishizawa, Nakura	Library characterizer for open-source VLSI design